FPGA Design Tip: How to Automatically Identify Your Build Time

FPGA design engineers compile a lot of images – fixing this, testing that. With multiple bitstreams loaded during system integration, it can be confusing which gateware (what we like to call “FPGA source code”) revision is the working image and which image is actually in the part.

Including a software-accessible, read-only register containing the date and time the FPGA was compiled is a great way for software to query the FPGA to see which gateware revision is currently in the part.

The only problem is that when this value is hard coded, we designers sometimes forget to update it which can cause confusion, or even the wrong software to be used. Tool Command Language (Tcl) can help. and if you’re using Xilinx Vivado, this is how (if you’re a Tcl guru, this will be old hat – but if you’re new to Tcl, this could save you a lot of headaches).

Steps to Use Tcl with Xilinx Vivado

1) A simple .tcl script can be automatically invoked pre-synthesis to update your compilation date and time so you never have to think about it. Start by making a file called setCompileTime.tcl that contains the following line only: 

set compileTime [clock format [clock seconds] -format {32’h%y%m%d%H}]

2) In Vivado, go to Synthesis settings, click on tcl.pre and navigate to your setCompileTime.tcl file. In the same settings window, under the “More options” field, include this text:

-generic COMPILATION_DATECODE=$compileTime

3) Now, in your Verilog top level, make a local parameter called COMPILATION_DATECODE as shown below:

localparam COMPILATION_DATECODE = 32’h00000000;

4) Connect this parameter value to your 32-bit read-only register and you’re done! Whenever Vivado runs synthesis, setCompileTime.tcl will run and create a variable calledcompileTime that contains the current date and time in the following format: YYMMDDHH (in 24-hour time format where 4pm would show up as “16”).

When synth_design (a Vivado tcl command) is run, the –generic command sets your local parameter, called COMPILATION_DATECODE, to the value compileTime that your script just created. All of this happens automatically and you never have to worry about forgetting to update your date code manually after an eight hour compile marathon! You can also do this with Synplify Pro and ISE, by using a slightly different Tcl command. The .tcl file contains:

set compileTime [clock format [clock seconds] -format {32’h %y%m%d%H}]
set_option -hdl_param -set COMPILATION_DATECODE $compileTime

5) And the ISE project contains the following line in the “Other Synplify Command Line Options” box:

run_tcl ./tcl/setCompileTime.tcl

Your Verilog is the same as described above. A quick internet search can also show you how to adapt this concept for VHDL, since the syntax is slightly different.

Hopefully this technique saves you time and headache, and helps software, firmware and gateware stay in agreement during the system integration process of your FPGA design.