NUVATION | Serial ATA (SATA) IP Core for Altera Devices

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Serial ATA (SATA) IP Core for Altera Devices


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Customer Remarks

	“Nuvation has been a select member of our Certified Design Center program for several years, as well as a design services vendor to Altera. We have been consistently impressed with the caliber of their organization, the time-to-market acceleration that they enable, and their strong track record across our broad customer base.” -- Altera


	"Nuvation has been a long standing Xilinx XPERT partner and consistently delivers leading edge designs and rapid design cycles for our OEM customers.” -- Xilinx


	"Nuvation recently helped us to complete a complex design. The combination of Nuvations design experience with FPGA's and our engineering and design expertise with Analog-to-Digital Converters created a very useful test and characterization solution for one of our new series of data converters. It is fun working with Nuvation. They met all expectations." -- Texas Instruments

FPGA · ASIC Partners

	Altera CDC
	Altera High-Speed I/O
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Technical Publications

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Product Brief

Features | Block Diagram | Contact |

Description

The Nuvation SATA IP Core is a drop-in core used to interface between memory or memory mapped I/O and SATA devices. The core includes the transport and link layers of a host controller, or host bus adapter (HBA). The core is compliant with the Serial ATA Advanced Host Controller Interface (AHCI) specification when implemented with an external PHY. AHCI is a native Serial ATA interface that simplifies the HBA down to a data-mover, while providing a clean mechanism for command queuing. The SATA IP core from Nuvation is available either as an encrypted Netlist or as a source code license. The Nuvation SATA core features an Avalon interface for easy integration in SOPC Builder.

Features

Compliant to the Serial ATA AHCI 1.0 specification, with 32 command slots per port, and 1 port per HBA
Supports all ATA/ATAPI commands, using both DMA and PIO protocols
4 clock domains: system, link/transport layer, transmit and receive
Spread-spectrum clocking supported by external PHY
Avalon bus interface, integrated into SOPC Builder
32-bit internal buses in link and transport layers
CONT primitive and “junk-data” scrambler to reduce EMI
Partitioned for two PHY variants: external or target-specific MGT
FIFOs between each architecture layer
Shallow link-phy FIFOs for phase/frequency variations in external PHY
Shallow transport-link FIFOs for flow control and temporary storage
Deep DMA controller FIFOs for data-rate matching
Supports basic AHCI capabilities: native command queuing, command-list override, and PIO multiple DRQ Block

Target Device

Altera Cyclone, Cyclone II, Stratix, Stratix II
Number of LE's: 4800
Number of Memory Bits: 23,680

Block Diagram

Contact

For more information please fill out the IP inquiry form or contact us by email at ip@nuvation.com.

Please download the product brief.