GFP-F IP Core  
How to Engage
IP Licensing & Purchasing
Get a Quote
Ask a Question
Customer Remarks

“Nuvation has been a select member of our Certified Design Center program for several years, as well as a design services vendor to Altera. We have been consistently impressed with the caliber of their organization, the time-to-market acceleration that they enable, and their strong track record across our broad customer base.”
-- Altera

"Nuvation has been a long standing Xilinx XPERT partner and consistently delivers leading edge designs and rapid design cycles for our OEM customers.”
-- Xilinx

"Nuvation recently helped us to complete a complex design. The combination of Nuvations design experience with FPGA's and our engineering and design expertise with Analog-to-Digital Converters created a very useful test and characterization solution for one of our new series of data converters. It is fun working with Nuvation. They met all expectations."
-- Texas Instruments

FPGA · ASIC Partners
Altera CDC

Altera High-Speed I/O

Altera DSP
Altera AMPP
Altera HardCopy Design Center
Lattice LEADER
QuickLogic QuickDR
Synplicity Certified Design Center
Xilinx XPERT
Xilinx Virtex-II Pro Early Adopter
Technical Publications
Accelerate Time to Market
Ethernet over SONET
FPGA Video Processing
   
Frame Mapped GFP IP Core

Features | Block Diagram | Device Utilization | Contact |


Description

The GFP-F IP Core receives and maps entire client signal frames into one GFP frame adhering to the format set out for the frame-mapped GFP mode of client signal adaptation. The GFP-F Core encapsulates entire octet-aligned, variable-length client signal frames into one GFP frame. The core is available for Altera Stratix, Stratix-II, Stratix GX / II GX, Cyclone, and Cyclone-II devices and utilizes an Altera-standard Atlantic interface. There is also a microcontroller register interface for parameter setting and status monitoring.

Features

  • Fully Compliant with Frame Mapped GFP Specification from ITU-T
  • GFP Control Frames are supported at a maximum of 10% of full line-rate
  • Encapsulator receives frames from multiple channels and individually maps frames into single GFP frames
  • Decapsulator receives frame-mapped GFP frames, and removes various GFP-unique fields
  • GFP and Ethernet configuration and status signals are available, and can be mapped to any micro-controller interface
  • Parameter and status signals included, to connected the core to a CPU-like interface, such as 8051 or I²C
  • Extension Header supports a Linear (Point-to-Point) connection. Other topologies supported with modifications.
  • Minimum packet-size is 32 bytes
  • Control frames always have higher priority than user data frames / packets
  • The inter-packet gap at the Ingress input must be a minimum of 2 cycles
  • Atlantic Interface: Datapath interfaces to the 64-bit Atlantic Specification at 50 MHz

Block Diagram



Device Utilization
Target Device Speed Grade Utilization 64-bit Data Performance
    LEs Memory Bits  
Altera Stratix EP1S -5 5862 21704 61.42
Cyclone II EP2C -7 4942 21704 61.61
    ALMs Memory Bits  

Altera Stratix-II EP2S

-3 2161 21704 98.49

Contact
For more information please fill out the IP inquiry form or contact us by email at ip@nuvation.com.

Please download the product brief.

 
© Nuvation Research Corporation, 3590 North First Street, San Jose, California 95134, USA. All logos are property of respective corporations.