NUVATION | GEOS-10i IP Core

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GEOS-10i IP Core


	REFERENCE DESIGNS

	IP Camera & Video
·	IP Camera Mini
·	IP Camera PoE
·	Intelligent Video Server
·	Multichannel Video Front End

	Xilinx/TI DSP Video
·	Picture-in-Picture
·	Virtual Socket Adapter

	Laser Diode Driver
·	Sequoia Analog
·	Sequoia-II Digital


	FPGA IP CORES

	Data over SONET
·	GEOS-10
·	GEOS-10i
·	GEOS-2
·	GEOS-2+2
·	GFP-F
·	GFP-T

	Storage Host Controllers
·	ATA-4 for Altera
·	ATA-5 for Altera
·	ATA-4 for Altera SOPC
·	ATA-5 for Altera SOPC
·	ATA-4 for Xilinx
·	ATA-5 for Xilinx
·	ATA-4 OPB for Xilinx
·	ATA-5 OPB for Xilinx
·	SATA for Xilinx


	THIRD PARTY IP

·	TI Digital Media Software


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Customer Remarks

	“Nuvation has been a select member of our Certified Design Center program for several years, as well as a design services vendor to Altera. We have been consistently impressed with the caliber of their organization, the time-to-market acceleration that they enable, and their strong track record across our broad customer base.” -- Altera


	"Nuvation has been a long standing Xilinx XPERT partner and consistently delivers leading edge designs and rapid design cycles for our OEM customers.” -- Xilinx


	"Nuvation recently helped us to complete a complex design. The combination of Nuvations design experience with FPGA's and our engineering and design expertise with Analog-to-Digital Converters created a very useful test and characterization solution for one of our new series of data converters. It is fun working with Nuvation. They met all expectations." -- Texas Instruments

FPGA · ASIC Partners

	Altera CDC
	Altera High-Speed I/O
	Altera DSP
	Altera AMPP
	Altera HardCopy Design Center
	Lattice LEADER
	QuickLogic QuickDR
	Synplicity Certified Design Center
	Xilinx XPERT
	Xilinx Virtex-II Pro Early Adopter

Technical Publications

	Accelerate Time to Market
	Ethernet over SONET
	FPGA Video Processing

Gigabit Ethernet to SONET OC-192 Multiplexer
(for Cortina Systems Chipset)

Features | Block Diagram | Ingress | Egress | Contact |

Description

The GEOS-10i IP core multiplexes up to 10 channels of GE traffic into a single Packet over SONET (POS) stream, using frame-mapped GFP (Generic Framing Procedures). A GEOS-8i variant has also been developed and implemented for 8xGbE to SONET. The GEOS-10i core is designed to interface with the Cortina® IXF1110 10-Port Gigabit Ethernet MAC and IXF1810x family of 10Gbit/s LAN/WAN Physical Layer Devices, using POS-PHY Level 4 cores.

Features

Supports up to OC-192 bandwidth
Multiplexes up to 10 ports of Gigabit Ethernet traffic into SONET
Supports Jumbo Packets
Configurable destination port address
Complies with Frame Mapped Generic Framing Procedures from ITU-T
A Link Layer function
Provides GbE Traffic Statistics per port
Plug & Play with POS-PHY Level 4 or POS-PHY Level 3 cores for variety of system solutions with different bandwidths
Optimized for integration with a 10-Port Gigabit Ethernet MAC (Cortina® IXF1110, PMC-Sierra PM3388 S/UNI® - 10xGE) and a 10Gbit/s LAN/WAN Physical Layer Device (Cortina® IXF1810x family, PMC-Sierra PM5390 S/UNI® -9953), using POS-PHY Level 4 cores
Verilog HDL register transfer level (RTL) code available
Available on Altera and Xilinx platforms

Block Diagram

Ingress: Ethernet-to-SONET Data Flow

Controlled by ESMUX module
Automatic generation of GFP header to packet w/ destination port ID
Pause information transfer to destination ports

Egress: SONET-to-Ethernet Data Flow

Controlled by SEDEMUX module
De-multiplexes traffic from SONET side into 10 GE ports
Routes packets to their corresponding ports
Extracts pause information from control packets
Asserts/de-asserts "pause" signal on each GE port

Contact

For more information please fill out the IP inquiry form or contact us by email at ipcores@nuvation.com.

Please read the press release or download the product brief.